ASPDAC 2007 - PDF Preprint Papers

ASPDAC 2007 Asia and South Pacific Design Automation Conference

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ASPDAC-2007 Paper

click to vote

ASPDAC
2007
ACM

185views Hardware» more ASPDAC 2007»

Exploration of Low Power Adders for a SIMD Data Path

14 years 4 months ago

Download www.cecs.uci.edu

Giacomo Paci, Paul Marchal, Luca Benini

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	185	Exploration of Low Power Adders for a SIMD Data Path	claim
2	174	Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems	claim
3	164	Thermal-Aware 3D IC Placement Via Transformation	claim
4	158	Symbolic Model Checking of Analog/Mixed-Signal Circuits	claim
5	156	PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation Tool	claim
6	156	Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture	claim
7	152	A Graph Reduction Approach to Symbolic Circuit Analysis	claim
8	146	Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos	claim
9	144	Control-Flow Aware Communication and Conflict Analysis of Parallel Processes	claim
10	144	Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method	claim
11	144	Design Methodology for 2.4GHz Dual-Core Microprocessor	claim
12	140	An Architecture for Combined Test Data Compression and Abort-on-Fail Test	claim
13	139	Deeper Bound in BMC by Combining Constant Propagation and Abstraction	claim
14	137	Delay Uncertainty Reduction by Interconnect and Gate Splitting	claim
15	136	A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction	claim
16	136	Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies	claim
17	135	Architectural Optimizations for Text to Speech Synthesis in Embedded Systems	claim
18	135	A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications	claim
19	133	Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM	claim
20	133	RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip	claim
21	132	FastRoute 2.0: A High-quality and Efficient Global Router	claim
22	132	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach	claim
23	131	Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign	claim
24	130	ARM MPCore; The streamlined and scalable ARM11 processor core	claim
25	130	A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses	claim
26	130	Configurable Multi-Processor Platforms for Next Generation Embedded Systems	claim
27	129	ECO-system: Embracing the Change in Placement	claim
28	124	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands	claim
29	124	BddCut: Towards Scalable Symbolic Cut Enumeration	claim
30	123	Creating Explicit Communication in SoC Models Using Interactive Re-Coding	claim
31	123	Coupling-aware Dummy Metal Insertion for Lithography	claim
32	122	A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications	claim
33	122	Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect	claim
34	121	Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches	claim
35	121	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI	claim
36	121	Approximation Algorithm for Process Mapping on Network Processor Architectures	claim
37	121	Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks	claim
38	120	Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost	claim
39	119	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space	claim
40	117	Short-Circuit Compiler Transformation: Optimizing Conditional Blocks	claim
41	117	Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)	claim
42	117	A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms	claim
43	116	VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond	claim
44	116	MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip	claim
45	116	A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield	claim
46	116	Frequency Selective Model Order Reduction via Spectral Zero Projection	claim
47	116	Safe Delay Optimization for Physical Synthesis	claim
48	116	DFM/DFY practices during physical designs for timing, signal integrity, and power	claim
49	116	Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS	claim
50	115	Model-based Programming Environment of Embedded Software for MPSoC	claim
51	115	Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware	claim
52	114	Automating Logic Rectification by Approximate SPFDs	claim
53	114	Approaching Speed-of-light Distortionless Communication for On-chip Interconnect	claim
54	112	Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid	claim
55	110	Fast Placement Optimization of Power Supply Pads	claim
56	110	High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs	claim
57	109	Communication Architecture Synthesis of Cascaded Bus Matrix	claim
58	109	On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design	claim
59	108	RunBasedReordering: A Novel Approach for Test Data Compression and Scan Power	claim
60	108	Software Performance Estimation in MPSoC Design	claim
61	108	Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes	claim
62	108	Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling	claim
63	108	Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation	claim
64	107	A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture	claim
65	107	Advanced tools for simulation and design of oscillators/PLLs	claim
66	106	Bisection Based Placement for the X Architecture	claim
67	105	An Efficient Computation of Statistically Critical Sequential Paths Under Retiming	claim
68	103	Towards scalable and secure execution platform for embedded systems	claim
69	103	Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems	claim
70	102	Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains	claim
71	101	A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects	claim
72	101	Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic	claim
73	101	Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies	claim
74	101	Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses	claim
75	101	Configurable AMBA On-Chip Real-Time Signal Tracer	claim
76	100	Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC	claim
77	100	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning	claim
78	99	Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion	claim
79	99	DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm	claim
80	99	Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores	claim
81	98	Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation	claim
82	98	Fast Analytic Placement using Minimum Cost Flow	claim
83	98	Node Mergers in the Presence of Don't Cares	claim
84	98	Fixing Design Errors with Counterexamples and Resynthesis	claim
85	98	Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies	claim
86	98	A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation	claim
87	97	FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control	claim
88	97	A Wideband CMOS LC-VCO Using Variable Inductor	claim
89	96	A Novel Performance-Driven Topology Design Algorithm	claim
90	96	Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers	claim
91	95	Optimization of Arithmetic Datapaths with Finite Word-Length Operands	claim
92	95	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits	claim
93	95	Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"	claim
94	95	Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future"	claim
95	94	A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates	claim
96	94	Overview on Low Power SoC Design Technology	claim
97	93	Flow-Through-Queue based Power Management for Gigabit Ethernet Controller	claim
98	93	DFM reality in sub-nanometer IC design	claim
99	93	Retiming for Synchronous Data Flow Graphs	claim
100	92	Numerical Function Generators Using Edge-Valued Binary Decision Diagrams	claim
101	92	Signal-to-Memory Mapping Analysis for Multimedia Signal Processing	claim
102	92	New Block-Based Statistical Timing Analysis Approaches Without Moment Matching	claim
103	92	Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation	claim
104	91	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs	claim
105	90	A 1Tb/s 3W Inductive-Coupling Transceiver Chip	claim
106	90	Protocol Transducer Synthesis using Divide and Conquer approach	claim
107	90	Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability	claim
108	89	Structured Placement with Topological Regularity Evaluation	claim
109	89	Fast Electrical Correction Using Resizing and Buffering	claim
110	89	Flow Time Minimization under Energy Constraints	claim
111	89	Trace Compaction using SAT-based Reachability Analysis	claim
112	88	Voltage Island Generation under Performance Requirement for SoC Designs	claim
113	88	A Run-Time Memory Protection Methodology	claim
114	88	Logic and Layout Aware Voltage Island Generation for Low Power Design	claim
115	87	A Retargetable Software Timing Analyzer Using Architecture Description Language	claim
116	87	An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools	claim
117	87	Topology exploration for energy efficient intra-tile communication	claim
118	87	WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design	claim
119	86	Fast Buffered Delay Estimation Considering Process Variations	claim
120	85	Runtime leakage power estimation technique for combinational circuits	claim
121	85	Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes	claim
122	84	Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms	claim
123	83	Design Consideration of 6.25 Gbps Signaling for High-Performance Server	claim
124	83	Improving Execution Speed of FPGA using Dynamically Reconfigurable Technique	claim
125	83	Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency	claim
126	82	Low-Power High-Speed 180-nm CMOS Clock Drivers	claim
127	82	Fast Buffer Insertion for Yield Optimization Under Process Variations	claim
128	82	Abstract, Multifaceted Modeling of Embedded Processors for System Level Design	claim
129	82	Efficient BMC for Multi-Clock Systems with Clocked Specifications	claim
130	82	Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation	claim
131	81	CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time	claim
132	81	LEAF: A System Level Leakage-Aware Floorplanner for SoCs	claim
133	81	Fault Dictionary Size Reduction for Million-Gate Large Circuits	claim
134	80	Recognition of Fanout-free Functions	claim
135	80	Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic	claim
136	79	A High-Throughput Low-Power AES Cipher for Network Applications	claim
137	79	Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS Circuits	claim
138	79	Multithreaded SAT Solving	claim
139	79	Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets	claim
140	78	A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost	claim
141	78	Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation	claim
142	78	Fast and Accurate OPC for Standard-Cell Layouts	claim
143	77	Hippocrates: First-Do-No-Harm Detailed Placement	claim
144	75	Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection	claim
145	75	Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form	claim
146	74	A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks	claim
147	69	A Multi-Drop Transmission-Line Interconnect in Si LSI	claim
148	68	System Architecture for Software Peripherals	claim
149	67	Synthesis of Reversible Sequential Elements	claim
150	67	SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design	claim
151	64	Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers