Implementing Caches in a 3D Technology for High Performance Processors

3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication involves stacking two or more die connected with a very high-density and low-latency interface. The die-to-die vias that comprise this interface can be treated like regular on-chip metal due to their small size (on the order of 1µm) and high speed (sub-FO4 die-to-die communication delay). The increased device density and the ability to place and route in the third dimension provide new opportunities for microarchitecture design. In this paper, we first present a brief overview of 3D integration technology. We then focus on the design of onchip caches using 3D integration. In particular, we show that the dense die-to-die vias enable caches that are 3Dpartitioned at the level of individual wordlines or bitlines. This results in a wire length reduction within SRAM arrays, and a reduction in the footprint of indivi...

• Type: Conference
• Year: 2005
• Where: ICCD
• Authors: Kiran Puttaswamy, Gabriel H. Loh
• Keywords: Hardware, ICCD 2005, Individual Sram Banks, Vias Enable Caches, Wire Length Reduction