Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines

One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelines. As several studies show, internal processor structures scale differently with decreasing device sizes. While in some cases the access latency is determined by the speed of the logic circuitry, for others it is dominated by the interconnect delay. Furthermore, while some stages can be super-pipelined with relatively small performance loss, others must be kept atomic. This paper proposes a possible solution to this problem, avoiding the traditional trade-off between parallelism and clock speed. First, allowing instructions to enter and leave the Issue Window in an asynchronously manner enables faster speeds in the front-end at the expense of small synchronization latencies. Second, using an Execution Cache for storing instructions that are already scheduled allows for bypassing the issue circuitry and thus ...

• Type: Conference
• Year: 2005
• Where: ISCA
• Authors: Emil Talpes, Diana Marculescu
• Keywords: Hardware, Internal Processor Structures, ISCA 2005, Microarchitecture Designers, Small Synchronization Latencies