ISCA 2005 - PDF Preprint Papers

ISCA 2005 International Symposium on Computer Architecture

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ISCA
2005
IEEE

181views Hardware» more ISCA 2005»

Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors

14 years 5 months ago

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With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...

Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...

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Id	Views	Title	Status

1	181	Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors	claim
2	172	An Ultra Low Power System Architecture for Sensor Network Applications	claim
3	166	Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines	claim
4	162	Mitigating Amdahl's Law through EPI Throttling	claim
5	154	Temporal Streaming of Shared Memory	claim
6	147	Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling	claim
7	144	Scalable Load and Store Processing in Latency Tolerant Processors	claim
8	141	RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence	claim
9	135	Deconstructing Commodity Storage Clusters	claim
10	134	An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors	claim
11	134	A High Throughput String Matching Architecture for Intrusion Detection and Prevention	claim
12	131	BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging	claim
13	128	An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures	claim
14	126	A Tree Based Router Search Engine Architecture with Single Port Memories	claim
15	121	Direct Cache Access for High Bandwidth Network I/O	claim
16	119	Microarchitecture of a High-Radix Router	claim
17	119	Rescue: A Microarchitecture for Testability and Defect Tolerance	claim
18	118	Continuous Optimization	claim
19	117	Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization	claim
20	115	RENO - A Rename-Based Instruction Optimizer	claim
21	115	The V-Way Cache: Demand Based Associativity via Global Replacement	claim
22	113	Piecewise Linear Branch Prediction	claim
23	105	Exploiting Structural Duplication for Lifetime Reliability Enhancement	claim
24	104	Opportunistic Transient-Fault Detection	claim
25	101	Virtualizing Transactional Memory	claim
26	101	Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks	claim
27	99	Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking	claim
28	99	Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management	claim
29	99	Store Buffer Design in First-Level Multibanked Data Caches	claim
30	98	Techniques for Efficient Processing in Runahead Execution Engines	claim
31	93	Analysis of the O-GEometric History Length Branch Predictor	claim
32	92	Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection	claim
33	91	High Efficiency Counter Mode Security Architecture via Prediction and Precomputation	claim
34	90	Optimizing Replication, Communication, and Capacity Allocation in CMPs	claim
35	88	Architecture for Protecting Critical Secrets in Microprocessors	claim
36	87	A Robust Main-Memory Compression Scheme	claim
37	81	The Impact of Performance Asymmetry in Emerging Multicore Architectures	claim
38	81	Improving Program Efficiency by Packing Instructions into Registers	claim
39	81	Energy Optimization of Subthreshold-Voltage Sensor Network Processors	claim
40	79	Design and Evaluation of Hybrid Fault-Detection Systems	claim

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