Increasing hardware efficiency with multifunction loop accelerators

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of singlefunction designs. In addition, the union approach to multifunction synthesis...

• Type: Conference
• Year: 2006
• Where: CODES
• Authors: Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke
• Keywords: CODES 2006, Loop Accelerator, Loop Nests, Multifunction Loop Accelerator, Software Engineering