Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty

One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and Vdd/Vth optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.

• Type: Conference
• Year: 2005
• Where: VLSID
• Authors: Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
• Keywords: Computer Architecture, Leakage Power, Leakage Reduction Techniques, Uncertainty Reduction, VLSID 2005