SMT processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is sig...
Ahmed Youssef, Mohamed Zahran, Mohab Anis, Mohamed...
Abstract--In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of f...
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Ha...
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultradeep submicrometer designs. To correctly predict performance/ leakage...
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the nee...
With scaling of Vt sub-threshold leakage power is increasing and expected to become significant part of total power consumption.In present work three new configurations of level s...
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is diss...
Abstract— As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unus...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...