An integrated debugging environment for reprogrammble hardware systems

Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the user’s design which allow the system to be monitored and updated at runtime. An assortment of logic is added before synthesis to allow variable buffering, assertion checking, and automatic breakpointing. Low-level clock control and access to off-chip storage is managed by a custom hardware operating system. Through the addition of these features, a system can be debugged directly on the hardware, bypassing simulation and reducing iterations through the design flow. Categories and Subject Descriptors: D.2.5 [Testing and Debugging]; B.5 [Register-Transfer Level Implementation]; B.6.3 [Design Aids]: Simulation, Verification General Terms: Design, Verification

• Type: Conference
• Year: 2005
• Where: AADEBUG
• Authors: Kevin Camera, Hayden Kwok-Hay So, Robert W. Brodersen
• Keywords: AADEBUG 2005, Hardware Operating System, Low-level Clock Control, Reprogrammable Hardware Systems, Software Engineering