Integrating buffer planning with floorplanning for simultaneous multi-objective optimization

As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, It is obviously infeasible to insert hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this paper, we derive the formulae of feasible regions, and integrate buffer planning with floorplanning to optimize area, timing, noise, and congestion (routability) simultaneously. In particular, we treat each buffer block as a soft module and apply Lagrangian relaxation to optimize the floorplan area. Experimental results show that our method obtains an average success rate ...

• Type: Conference
• Year: 2004
• Where: ASPDAC
• Authors: Yi-Hui Cheng, Yao-Wen Chang
• Keywords: ASPDAC 2004, Buffer Insertion, Decouple Coupling Effects, Deep Submicron Era