Integration of VHDL into a system design environment

Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers a high performance clock period precision simulation, according to the SDF simulation paradigm. Furthermore it supports mixed mode (e.g. VHDL) simulations via coupling to external simulators, and via cross-compiling.

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Ludwig Schwoerer, Matthias Lück, Hartmut Schröder
• Keywords: EURODAC 1995, Image Sequence Simulations, Period Precision Simulation, SDF Simulation Paradigm, VHDL