A three level software system for thermal analysis of semiconductor devices, one-chip monolith IC's, multi-chip modules (MCM) and hybrid IC's is presented. For each desig...
Konstantin O. Petrosjanc, I. A. Kharitonov, N. I. ...
A new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity a...
A somewhat novel approach is presented for determining FSM state codes. Instead of producing an assignment designed to minimise the overall logic of the machine, all Moore outputs...
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and glo...
Michael J. Alexander, James P. Cohoon, Joseph L. G...
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
The paper presents an approach for performance and complexity analysis of hardware/software implementations for real-time systems on every stage of the partitioning. There are two...
The synthesis of electronic circuits on system level o ers the possibility to nd better locations of the A/D interfaces and to determine parameters like clock rates and bit widths...
Due to the ever increasing complexity of electronic system (ES) design, the conceptual design phase and its realization in later phases of the design stream have become increasing...