Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

79

Voted

ASYNC
2006
IEEE

68views Hardware» more ASYNC 2006»

Interface Design for Rationally Clocked GALS Systems

15 years 9 months ago

Interface Design for Rationally Clocked GALS Systems

Download tima.imag.fr

Joycee Mekie, Supratik Chakraborty, Dinesh K. Shar

Real-time Traffic

ASYNC 2006 | Hardware |

claim paper

Related Content

» System level power and performance modeling of GALS pointtopoint communication interfaces

» Design space exploration of a mesochronous link for costeffective and flexible GALS NOCs

» Point to Point GALS Interconnect

» Performance Evaluation of Elastic GALS Interfaces and Network Fabric

» Clock Synchronization through Handshake Signalling

» SystemJ A GALS language for system level design

» Enhanced GALS Techniques for Datapath Applications

» Performance and Power Analysis of Globally Asynchronous Locally Synchronous MultiProcessor...

» A LowArea MultiLink Interconnect Architecture for GALS Chip Multiprocessors

Post Info
More Details (n/a)

Added	10 Jun 2010
Updated	10 Jun 2010
Type	Conference
Year	2006
Where	ASYNC
Authors	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan

Comments (0)