Interval-based models for run-time DVFS orchestration in superscalar processors

We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under various frequency and voltage combinations and ii) implement targeted DVFS policies at run-time. The models analyze program execution in intervals —steady-state and miss-event intervals. Intervals are signalled by miss events (L2-misses in our case) that upset the “steady state” execution of the program and are ended when the pipeline reaches again a steady state. The first model is fed by an approximation of the stall cycles (the time the processor instruction window is blocked) due to long-latency L2-misses. The second model improves on this approximation using as input the occupancy of the L2's miss-handling registers (MSHRs). Despite their simplicity these models prove to be accurate in predicting the performance (and energy) for any target frequency/voltage setting, yielding average errors of 2....

• Type: Conference
• Year: 2010
• Where: CF
• Authors: Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras
• Keywords: CF 2010, DVFS Policies, Miss-event Intervals, Steady State