I/O placement for FPGAs with multiple I/O standards

In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer linear programming formulation for the constrained I/O placement problem. The size of the integer linear program derived is independent of the number of I/O objects to be placed and hence is scalable to very large design instances. For example, for a Xilinx Virtex-E FPGA, the number of integer variables required is never more than 32 and is much smaller for practical design instances. Extensive experimental results using a non-commercial integer linear program solver shows that it only takes seconds to solve the resultant integer linear program in practice. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids; J.6 [Computer-Aided Engineering]: CAD General Terms Algorithms Keywords Placement, I/O placement, field-programmable gate array, I/O standards

• Type: Conference
• Year: 2003
• Where: FPGA
• Authors: Wai-Kei Mak
• Keywords: FPGA 2003, Hardware, I/O Placement, Integer Linear, Integer Linear Program