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29

ISSS
2000
IEEE

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IP Reuse in the System on a Chip Era

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IP Reuse in the System on a Chip Era

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Intellectual Property (IP) Reuse is one of the keys for System on a Chip (SoC) design productivity improvement. Although IP reuse has been explored both technically and as a business for many years, only recently systematic approaches based on EDA technology are starting to emerge in the marketplace. This paper gives an

Warren Savage, John Chilton, Raul Camposano

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Design Productivity Improvement | Hardware | Intellectual Property | IP Reuse | ISSS 2000 |

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Added	31 Jul 2010
Updated	31 Jul 2010
Type	Conference
Year	2000
Where	ISSS
Authors	Warren Savage, John Chilton, Raul Camposano

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