IP Reuse in the System on a Chip Era

Intellectual Property (IP) Reuse is one of the keys for System on a Chip (SoC) design productivity improvement. Although IP reuse has been explored both technically and as a business for many years, only recently systematic approaches based on EDA technology are starting to emerge in the marketplace. This paper gives an

• Type: Conference
• Year: 2000
• Where: ISSS
• Authors: Warren Savage, John Chilton, Raul Camposano
• Keywords: Design Productivity Improvement, Hardware, Intellectual Property, IP Reuse, ISSS 2000