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ISSS
2000
IEEE
129views Hardware» more  ISSS 2000»
13 years 11 months ago
IP Reuse in the System on a Chip Era
Intellectual Property (IP) Reuse is one of the keys for System on a Chip (SoC) design productivity improvement. Although IP reuse has been explored both technically and as a busin...
Warren Savage, John Chilton, Raul Camposano
FPL
2009
Springer
104views Hardware» more  FPL 2009»
13 years 11 months ago
A multi-layered XML schema and design tool for reusing and integrating FPGA IP
Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and veri...
Adam Arnesen, Nathan Rollins, Michael J. Wirthlin
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
14 years 7 months ago
Bridge Over Troubled Wrappers: Automated Interface Synthesis
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
Vijay D'Silva, S. Ramesh, Arcot Sowmya
DAC
1998
ACM
14 years 7 months ago
Watermarking Techniques for Intellectual Property Protection
Digital system designs are the product of valuable effort and knowhow. Their embodiments, from software and HDL program down to device-level netlist and mask data, represent caref...
Andrew B. Kahng, John Lach, William H. Mangione-Sm...