Large-scale Boolean matching

— We propose a methodology for Boolean matching under permutations of inputs and outputs (PP-equivalence checking problem) — a key step in incremental logic design that identifies large sections of a netlist that are not affected by a change in specifications. Finding reusable sections of a netlist reduces the amount of work in each design iteration and accelerates design closure. Our approach integrates graph-based, simulation-driven and SAT-based techniques to make Boolean matching feasible for large circuits. Experimental results confirm scalability of our techniques to circuits with hundreds and even thousands of inputs and outputs.

• Type: Conference
• Year: 2010
• Where: DATE
• Authors: Hadi Katebi, Igor L. Markov
• Keywords: DATE 2010, Hardware, Incremental Logic Design, Netlist, PP-equivalence Checking Problem