Layout Techniques for Minimizing On-Chip Interconnect Self Inductance

Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconnect topology. This long range sensitivity makes it di cult to balance delays in nets like clock trees, so for such nets inductance must be minimized. In this paper we use two- and threedimensional electromagnetic eld solvers to compare dedicated ground planes to a less area-consuming approach, interdigitatingthe signallinewithgroundlines. The surprising conclusion is that with very little area penalty, interdigitated ground lines are more e ective at minimizing self-inductance than ground planes.

• Type: Conference
• Year: 1998
• Where: DAC
• Authors: Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob White
• Keywords: DAC 1998, Dedicated Ground Planes, Design Automation, Nets Inductance, Threedimensional Electromagnetic Eld