Leakage control in FPGA routing fabric

Abstract— As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unused multiplexers used in the interconnect fabric. This work focuses on reducing the leakage of these unused multiplexers by controlling their inputs. We investigate the design issues involved in implementing such a technique and also show experimental results demonstrating the effectiveness of our approach.

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
• Keywords: ASPDAC 2005, FPGA Leakage, Hardware, Leakage Power, Unused Multiplexers