Lightweight runtime control flow analysis for adaptive loop caching

Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level one cache. However, due to code structure restrictions and/or costly design time pre-analysis efforts, previous loop cache designs are not suitable for all applications and system scenarios. In this paper, we present an adaptive loop cache that is amenable to a wide range of system scenarios, providing an additional 20% average instruction memory hierarchy energy savings (with individual benchmark energy savings as high as 69%) compared to the best previous loop cache design. Categories and Subject Descriptors B.3.2 [Hardware]: Memory Structures: Design Styles – cache memories. General Terms Design. Keywords Loop cache, low energy, architecture tuning, embedded systems.

• Type: Conference
• Year: 2010
• Where: GLVLSI
• Authors: Marisha Rawlins, Ann Gordon-Ross
• Keywords: GLVLSI 2010, Loop Cache, Loop Cache Design, Memory Hierarchy Energy, VLSI