GLVLSI 2010 - PDF Preprint Papers

GLVLSI 2010 Great Lakes Symposium on VLSI

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed GLVLSI-2010 Paper

click to vote

GLVLSI
2010
IEEE

310views VLSI» more GLVLSI 2010»

Graphene tunneling FET and its applications in low-power circuit design

14 years 5 months ago

Download www.ece.rice.edu

Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...

Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Moh...

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	310	Graphene tunneling FET and its applications in low-power circuit design	claim
2	299	A low-offset high-speed double-tail dual-rail dynamic latched comparator	claim
3	296	Synthetic biology: from modules to systems	claim
4	296	AOP-based high-level power estimation in SystemC	claim
5	234	On-chip point-of-load voltage regulator for distributed power supplies	claim
6	220	Thermal-aware voltage droop compensation for multi-core architectures	claim
7	212	An integrated thermal estimation framework for industrial embedded platforms	claim
8	210	Overscaling-friendly timing speculation architectures	claim
9	209	Enhancing debugging of multiple missing control errors in reversible logic	claim
10	190	A linear statistical analysis for full-chip leakage power with spatial correlation	claim
11	189	8Gb/s capacitive low power and high speed 4-PWAM transceiver design	claim
12	187	Write activity reduction on flash main memory via smart victim cache	claim
13	183	Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors	claim
14	178	Improving the testability and reliability of sequential circuits with invariant logic	claim
15	172	Online convex optimization-based algorithm for thermal management of MPSoCs	claim
16	171	Timing-driven variation-aware nonuniform clock mesh synthesis	claim
17	168	A revisit to voltage partitioning problem	claim
18	164	Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs	claim
19	161	Electromagnetic interaction of on-chip antennas and CMOS metal layers for wireless IC interconnects	claim
20	156	A multi-level approach to reduce the impact of NBTI on processor functional units	claim
21	154	Read-out schemes for a CNTFET-based crossbar memory	claim
22	154	Resource-constrained timing-driven link insertion for critical delay reduction	claim
23	152	Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems	claim
24	150	Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS	claim
25	149	Lightweight runtime control flow analysis for adaptive loop caching	claim
26	141	Energy-efficient redundant execution for chip multiprocessors	claim
27	139	Dynamically resizable binary decision diagrams	claim
28	138	Methodology to achieve higher tolerance to delay variations in synchronous circuits	claim
29	136	Thermal-aware compilation for system-on-chip processing architectures	claim
30	131	Clock skew reduction by self-compensating manufacturing variability with on-chip sensors	claim
31	119	Line width optimization for interdigitated power/ground networks	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers