LimitLESS Directories: A Scalable Cache Coherence Scheme

Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coherence. We propose the LimitLESS directory protocol to solve this problem. The LimitLESS scheme uses a combination of hardware and software techniques to realize the performance of a full-map directory with the memory overhead of a limited directory. This protocol is supported by Alewife, a large-scale multiprocessor. We describe the architectural interfaces needed to implement the LimitLESS directory, and evaluate its performance through simulations of the Alewife machine.

• Type: Conference
• Year: 1991
• Where: ASPLOS
• Authors: David Chaiken, John Kubiatowicz, Anant Agarwal
• Keywords: ASPLOS 1991, LimitLESS Directory, LimitLESS Directory Protocol, Memory Access Latency, Programming Languages