On load latency in low-power caches

Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional latency, instructions speculatively issued and dependent on a non-deterministic load must be re-executed. Our experiments show that there is a large performance degradation and associated energy wastage due to these effects of instruction re-execution. To address this problem, we propose an early cache set resolution scheme. It is based on the observation that the displacement values used for address generation are generally small. Our experimental evaluation shows that this technique is quite effective in mitigating this problem. Categories and Subject Descriptors: B.3 [Memory Structures]: Performance Analysis and Design Aids General Terms: Performance, experimentation

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John
• Keywords: Additional Latency, Cache Access Latency, ISLPED 2003, Large Performance Degradation