Load Miss Prediction - Exploiting Power Performance Trade-offs

— Modern CPUs operate at GHz frequencies, but the latencies of memory accesses are still relatively large, in the order of hundreds of cycles. Deeper cache hierarchies with larger cache sizes can mask these latencies for codes with good data locality and reuse, such as structured dense matrix computations. However, cache hierarchies do not necessarily benefit sparse scientific computing codes, which tend to have limited data locality and reuse. We therefore propose a new memory architecture with a Load Miss Predictor (LMP), which includes a data bypass cache and a predictor table, to reduce access latencies by determining whether a load should bypass the main cache hierarchy and issue an early load to main memory. Our architecture uses the L2 (and lower caches) as a victim cache for data removed from our bypass cache. We use cycleaccurate simulations, with SimpleScalar and Wattch to show that our LMP improves the performance of sparse codes, our application domain of interest, on a...

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Konrad Malkowski, Greg M. Link, Padma Raghavan, Mary Jane Irwin
• Keywords: Bypass Cache, Cache, Cache Hierarchies, Distributed And Parallel Computing, IPPS 2007