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VTC
2008
IEEE

Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism

14 years 6 months ago
Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with quasi-cyclic (QC) LDPC codes at long block lengths. A modified progressive edge-growth algorithm is used to construct the hierarchical quasi-cyclic (H-QC) LDPC codes. By adding implementation-friendly two-level hierarchy with limited types of second-level submatrices in the parity check matrix, coding performance is improved substantially over QC codes. We also show that QC-based decoder architecture can be easily applied to H-QC decoders to achieve better coding gain and higher throughput performance. Moreover, the degree of decoding parallelism and code length can be adjusted by changing the HQC code construction parameters. Keywords-Low-density parity-check code; quasi-cyclic (QC) codes; progressive edge-growth (PEG); partially-parallel decoder
Chia-Yu Lin, Mong-Kai Ku, Yi-Hsing Chien
Added 01 Jun 2010
Updated 01 Jun 2010
Type Conference
Year 2008
Where VTC
Authors Chia-Yu Lin, Mong-Kai Ku, Yi-Hsing Chien
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