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GLOBECOM
2006
IEEE
14 years 6 months ago
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...
VTC
2008
IEEE
124views Communications» more  VTC 2008»
14 years 6 months ago
Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with qu...
Chia-Yu Lin, Mong-Kai Ku, Yi-Hsing Chien