LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs

This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the following limitations of current communication architectures: (i) lack of control over the allocation of communication bandwidth to different system components or data flows (e.g., in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the communication requests (e.g., in time division multiplexed access (TDMA) based architectures), sometimes leading to larger latencies for high-priority communications. We present two variations of LOTTERYBUS: the first is a low overhead architecture with statically configured parameters, while the second variant is a more sophisticated architecture, in which values of the architectural parameters are allowed to vary dynamically. Our experiments i...

• Type: Conference
• Year: 2001
• Where: DAC
• Authors: Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
• Keywords: Communication Latencies, Current Communication Architectures, DAC 2001, Design Automation, Priority Communication Traffic