Design guidelines for low- and ultra low-power arithmetic units are presented. We analyze structures for addition in the energy-delay space to determine the most suitable for these regions of operations. This paper demonstrates that the use of more complex highperformance structures combined with scaling of the supply-voltage outperforms traditional low-power oriented designs in the low- and ultra low-power domain.
Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdz