A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II

Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2m ) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m + 1 and the basic cell of our circuit design needs 5 latches (flip-flops). On the other hand, most of other multipliers of the same type have latency 3m and the basic cell of each multiplier needs 7 latches. Comparing the gates areas in each basic cell, we find that the hardware complexity of our multiplier is 25 percent reduced from the multipliers with 7 latches.

• Type: Conference
• Year: 2003
• Where: ARITH
• Authors: Soonhak Kwon
• Keywords: Applied Computing, ARITH 2003, Basic Cell, Hardware Complexity, Parallel Systolic Multiplier