A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting

—In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first

• Type: Journal
• Year: 2011
• Where: CCECE
• Authors: Kambiz Nanbakhsh, Hamidreza Maghami, Samad Sheikhaei, Nasser Masoumi, Pedram Payandehnia
• Keywords: ADC, CCECE 2011, Electrical And Computer Engineering, H Power, Power Consumption