Low power architecture of the soft-output Viterbi algorithm

CT This paper investigates the low power implementation issues of the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. By briefly explaining the theory of turbo codes, and by reviewing several of the decoding algorithms, we develop the computational requirements for a SOVA implementation, and ultimately develop an architecture that completes those computations with reduced power consumption. The architecture builds on previous work on the Viterbi and Soft-Output Viterbi algorithms, and incorporates a novel orthogonal access memory structure, which provides parallel access across sequentially received data.

• Type: Conference
• Year: 1998
• Where: ISLPED
• Authors: David Garrett, Mircea R. Stan
• Keywords: Hardware, ISLPED 1998, Low Power Implementation, Soft-output Viterbi Algorithms, Turbo Codes