ISLPED 1998 - PDF Preprint Papers

ISLPED 1998 International Symposium on Low Power Electronics and Design

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ISLPED
1998
ACM

155views Hardware» more ISLPED 1998»

Low threshold CMOS circuits with low standby current

14 years 5 months ago

Download www.cecs.uci.edu

Multi-Voltage CMOS MVCMOS is a design methodology for very low power supply voltages that uses low-threshold transistors in series with the supply rails. The control voltages on...

Mircea R. Stan

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Id	Views	Title	Status

1	155	Low threshold CMOS circuits with low standby current	claim
2	124	Recent developments in high integration multi-standard CMOS transceivers for personal communication systems	claim
3	110	A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances	claim
4	105	Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors	claim
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6	103	Integrated DC/DC converter with digital controller	claim
7	102	Low power methodology and design techniques for processor design	claim
8	102	Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits	claim
9	102	Memory modeling for system synthesis	claim
10	98	Minimum supply voltage for bulk Si CMOS GSI	claim
11	95	Low-power miniaturized information display systems	claim
12	95	A reconfigurable dual output low power digital PWM power converter	claim
13	95	The petrol approach to high-level power estimation	claim
14	94	Theoretical bounds for switching activity analysis in finite-state machines	claim
15	92	Towards the capability of providing power-area-delay trade-off at the register transfer level	claim
16	92	Power dissipated by CMOS gates driving lossless transmission lines	claim
17	92	Power consumption of parallel spread spectrum correlator architectures	claim
18	92	Decorrelating (DECOR) transformations for low-power adaptive filters	claim
19	90	CMOS front end components for micropower RF wireless systems	claim
20	89	Emerging power management tools for processor design	claim
21	88	Low-swing interconnect interface circuits	claim
22	86	The energy complexity of register files	claim
23	85	Estimation of maximum power supply noise for deep sub-micron designs	claim
24	84	Low power architecture of the soft-output Viterbi algorithm	claim
25	83	A three-port adiabatic register file suitable for embedded applications	claim
26	82	The simulation and evaluation of dynamic voltage scaling algorithms	claim
27	82	Low power and low voltage CMOS digital circuit techniques	claim
28	81	High performance DSPs - what's hot and what's not?	claim
29	80	Power calculation and modeling in deep submicron	claim
30	79	Voltage scheduling problem for dynamically variable voltage processors	claim
31	79	Low-energy embedded FPGA structures	claim
32	78	Monitoring system activity for OS-directed dynamic power management	claim
33	78	Power-delay tradeoffs for radix-4 and radix-8 dividers	claim
34	75	A power optimization method considering glitch reduction by gate sizing	claim
35	72	Power invariant vector compaction based on bit clustering and temporal partitioning	claim
36	69	A unified approach in the analysis of latches and flip-flops for low-power systems	claim
37	68	System-level power estimation and optimization	claim
38	68	Power exploration for dynamic data types through virtual memory management refinement	claim
39	67	Power and performance tradeoffs using various caching strategies	claim

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