A low-power bus design using joint repeater insertion and coding

In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies. We develop a methodology to calculate the repeater size and separation that minimize the total power dissipation for joint repeater insertion and coding for a specific delay target. This methodology is employed to obtain power vs. delay trade-offs for 130-nm, 90-nm, 65-nm, and 45-nm technology nodes. Using ITRS technology scaling data, we show that proposed technique provides 54%, 67%, and 69% power savings over optimally repeater-inserted 10-mm 32-bit bus at 90-nm, 65-nm, and 45-nm technology nodes, respectively, while achieving the same delay. Categories and Subject Descriptors: B.4.3 [Input/output and data communications]: Interconnections (Subsystems) General Terms: Design, Performance

• Type: Conference
• Year: 2005
• Where: ISLPED
• Authors: Srinivasa R. Sridhara, Naresh R. Shanbhag
• Keywords: 45-nm Technology Nodes, ISLPED 2005, Joint Repeater Insertion, Repeater Insertion