ISLPED 2005 - PDF Preprint Papers

ISLPED 2005 International Symposium on Low Power Electronics and Design

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ISLPED
2005
ACM

178views Hardware» more ISLPED 2005»

Energy efficient strategies for deployment of a two-level wireless sensor network

14 years 5 months ago

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We investigate and develop energy-efficient strategies for deployment of wireless sensor networks (WSN) for the purpose of monitoring some phenomenon of interest in a coverage reg...

Ali Iranli, Morteza Maleki, Massoud Pedram

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Id	Views	Title	Status

1	178	Energy efficient strategies for deployment of a two-level wireless sensor network	claim
2	150	Fast configurable-cache tuning with a unified second-level cache	claim
3	150	Instruction packing: reducing power and delay of the dynamic scheduling logic	claim
4	147	System level power and performance modeling of GALS point-to-point communication interfaces	claim
5	136	Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy	claim
6	123	Coordinated, distributed, formal energy management of chip multiprocessors	claim
7	122	A simple mechanism to adapt leakage-control policies to temperature	claim
8	119	FinFET-based SRAM design	claim
9	111	Energy reduction in multiprocessor systems using transactional memory	claim
10	111	Peak temperature control and leakage reduction during binding in high level synthesis	claim
11	110	Complexity reduction in an nRERL microprocessor	claim
12	109	Power reduction by varying sampling rate	claim
13	109	Accurate battery lifetime estimation using high-frequency power profile emulation	claim
14	108	Replacing global wires with an on-chip network: a power analysis	claim
15	103	A non-uniform cache architecture for low power system design	claim
16	103	A technique for low energy mapping and routing in network-on-chip architectures	claim
17	102	Snug set-associative caches: reducing leakage power while improving performance	claim
18	101	Energy-aware fetch mechanism: trace cache and BTB customization	claim
19	101	Defocus-aware leakage estimation and control	claim
20	100	A tunable bus encoder for off-chip data buses	claim
21	100	Joint exploration of architectural and physical design spaces with thermal consideration	claim
22	99	Self-timed circuits for energy harvesting AC power supplies	claim
23	99	A low-power bus design using joint repeater insertion and coding	claim
24	98	Synonymous address compaction for energy reduction in data TLB	claim
25	98	Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage	claim
26	96	Region-level approximate computation reuse for power reduction in multimedia applications	claim
27	96	Power-optimal repeater insertion considering Vdd and Vth as design freedoms	claim
28	96	A low-power, multichannel gated oscillator-based CDR for short-haul applications	claim
29	93	Power-aware code scheduling for clusters of active disks	claim
30	91	LAP: a logic activity packing methodology for leakage power-tolerant FPGAs	claim
31	90	Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices	claim
32	90	Driver pre-emphasis techniques for on-chip global buses	claim
33	88	PARE: a power-aware hardware data prefetching engine	claim
34	87	Runtime identification of microprocessor energy saving opportunities	claim
35	86	An evaluation of code and data optimizations in the context of disk power reduction	claim
36	85	Low-power fanout optimization using multiple threshold voltage inverters	claim
37	85	A low-power crossroad switch architecture and its core placement for network-on-chip	claim
38	84	Hierarchical power management with application to scheduling	claim
39	82	Dataflow analysis for energy-efficient scratch-pad memory management	claim
40	72	A low power current steering digital to analog converter in 0.18 Micron CMOS	claim
41	68	Low power SRAM techniques for handheld products	claim
42	68	Two efficient methods to reduce power and testing time	claim
43	63	Inter-program optimizations for conserving disk energy	claim

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