Low Power FPGA Implementations of 256-bit Luffa Hash Function

Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Two major gate level techniques are introduced in order to reduce the power consumption, namely the pipeline technique (with some variants) and the use of embedded RAM blocks instead of general purpose logic elements.

• Type: Conference
• Year: 2010
• Where: DSD
• Authors: Paris Kitsos, Nicolas Sklavos, Athanassios N. Skodras
• Keywords: DSD 2010, Hardware, Hash Function, Low Power Techniques, Major Gate Level