DSD 2010 - PDF Preprint Papers

DSD 2010 Euromicro Symposium on Digital Systems Design

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DSD
2010
IEEE

221views Hardware» more DSD 2010»

Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis

13 years 9 months ago

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Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...

Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...

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Id	Views	Title	Status

1	221	Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis	claim
2	190	Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance	claim
3	172	Adaptive Cache Memories for SMT Processors	claim
4	171	Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG	claim
5	162	A Parallel for Loop Memory Template for a High Level Synthesis Compiler	claim
6	161	Design of Trace-Based Split Array Caches for Embedded Applications	claim
7	153	Simulation of High-Performance Memory Allocators	claim
8	149	Low Latency Recovery from Transient Faults for Pipelined Processor Architectures	claim
9	144	On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism	claim
10	141	Adaptive Beamforming Using the Reconfigurable MONTIUM TP	claim
11	140	RobuCheck: A Robustness Checker for Digital Circuits	claim
12	140	Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications	claim
13	137	A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems	claim
14	135	An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits	claim
15	134	A New High-Level Methodology for Programming FPGA-Based Smart Camera	claim
16	133	Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints	claim
17	131	A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder	claim
18	126	Low Power FPGA Implementations of 256-bit Luffa Hash Function	claim
19	123	A Packet Classifier Using a Parallel Branching Program Machine	claim
20	121	Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA	claim
21	112	Re-NUCA: Boosting CMP Performance Through Block Replication	claim
22	111	Faults Coverage Improvement Based on Fault Simulation and Partial Duplication	claim
23	110	A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour	claim
24	99	Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies	claim

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