Low-power high-level synthesis for FPGA architectures

This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estimator closely reflects both dynamic and static power contributed by various FPGA components in 0.1um technology. The power estimation error is 16.2% on average. Second, we present a low power high level synthesis system, named LOPASS, for FPGA designs. It includes two algorithms for power consumption reduction: (i) a simulated annealing engine that carries out resource selection, function unit binding, scheduling, register binding, and data path generation simultaneously to effectively reduce power; (ii) an enhanced weighted bipartite matching algorithm that is able to reduce the total amount of MUX ports by 22.7%. Experimental results show that LOPASS is able to reduce power consumption by 35.8% compared to the results of Synopsys’ Behavioral Compiler. Categories and Subject Descriptors B.5.2 [Register-Trans...

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Deming Chen, Jason Cong, Yiping Fan
• Keywords: FPGA, ISLPED 2003, Power Estimation, Power Estimator