Low-power, low-complexity instruction issue using compiler assistance

In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achieve high performance. The logic that facilitates dynamic issue is one of the most power-hungry and time-critical components in a typical out-of-order issue processor. This paper develops a cooperative hardware/software technique to reduce complexity and energy consumption of the issue logic. The proposed scheme is based on the observation that not all instructions in a program require the same amount of dynamic reordering. Instructions that belong to basic blocks for which the compiler can perform near-optimal sche- duling do not need any intra-block instruction reordering but require only inter-block instruction overlap. In contrast, blocks where the compiler is limited by artificial dependences and memory misses require both intra-block and inter-block instruction reordering. The proposed ReorderSensitive Is...

• Type: Conference
• Year: 2005
• Where: ICS
• Authors: Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S. McKinley
• Keywords: Dynamic Issue, ICS 2005, Issue Queue, Out-of-order Issue Processor, Theoretical Computer Science