Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"

In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, hierarchical approaches from UniPhier Soc level, UniPhier Processor level, IPP (Instruction Parallel Processor) level, and Circuit level are adopted. As SoC level, 1) Well functionally isolated 5 major units of UniPhier SoC architecture, 2) Dedicated stream DMA controller which can minimize CPU load and memory access. As UniPhier Processor level, 1) UniPhier Processor consists of IPP with dedicated low power hardware engine, 2) VMP (Virtual Multi-Processor) mechanism with micro sleep which can reduce average power consumption in case of multiple tasks concurrent operation, 3) Intermittent operation with the combination of micro-sleep and clock/power down scheme in case of very light load operation. As IPP level, 1) Sophisticated instruction fetch buffer mechanism which can reduce more than 50% memory access fo...

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita
• Keywords: ASPDAC 2007, Hardware, Soc Level, UniPhier Processor Level, Uniphier Soc