Low power/area branch prediction using complementary branch predictors

Although high branch prediction accuracy is necessary for high performance, it typically comes at the cost of larger predictor tables and/or more complex prediction algorithms. Unfortunately, large predictor tables and complex algorithms require more chip area and have higher power consumption, which precludes their use in embedded processors. As an alternative to large, complex branch predictors, in this paper, we investigate adding complementary branch predictors (CBP) to embedded processors to reduce their power consumption and/or improve their branch prediction accuracy. A CBP differs from a conventional branch predictor in that it focuses only on frequently mispredicted branches while letting the conventional branch predictor predict the more predictable ones. Our results show that adding a small 16-entry (28 byte) CBP reduces the branch misprediction rate of static, bimodal, and gshare branch predictors by an average of

• Type: Conference
• Year: 2008
• Where: IPPS
• Authors: Resit Sendag, Joshua J. Yi, Peng-fei Chuang, David J. Lilja
• Keywords: Branch Prediction Accuracy, Branch Predictors, Conventional Branch Predictor, Distributed And Parallel Computing, IPPS 2008