Low swing dual threshold voltage domino logic

A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active power consumption is reduced by up to 9.4% while improving the noise immunity by 2.6% as compared to standard domino logic circuits. It is also shown that by applying a low swing contention reduction technique, the power savings can be further increased by 6.7% while the delay can be improved by 8.6%. A simple and efficient dual threshold voltage (dual-Vt) circuit technique that incorporates low swing signals is also proposed. It is shown that the proposed dual-Vt technique reduces the standby leakage current by approximately 235 times while offering enhanced delay characteristics as compared to a standard low threshold voltage implementation. Keywords Domino logic, low voltage swing, dual-Vt, low power, dynamic circuits.

• Type: Conference
• Year: 2002
• Where: GLVLSI
• Authors: Volkan Kursun, Eby G. Friedman
• Keywords: Domino Logic, GLVLSI 2002, Low Swing, Low Swing Domino, VLSI