Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications

Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical paths to maintain the performance. Mixed-Vth MVT static CMOS design technique allows di erent thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Di erent MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistorlevel threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20 more leakage reduction compared to the corresponding gate-level dual threshold technique.

• Type: Conference
• Year: 1999
• Where: DAC
• Authors: Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
• Keywords: Computer Architecture, DAC 1999, Dual Threshold Technique, Gate-level Dual Threshold, MVT CMOS