An LP-based methodology for improved timing-driven placement

— A method for timing driven placement is presented. The core of the approach is optimal timing-driven relaxed placement based on a linear programming (LP) formulation. The formulation captures all topological paths in a linear sized LP and thus, heuristic net weights or net budgets are not necessary. Additionally, explicit enumeration of a large number of paths is avoided. The flow begins with a given placement and iteratively extracts timing-critical sub-circuits, optimally places the sub-circuit by LP and applies a timing-driven legalizer. The approach is applied to the FPGA domain and yields an average of 19.6% reduction in clock period of routed MCNC designs versus [6] (with reductions up to 39.5%).

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal
• Keywords: ASPDAC 2005, Hardware, Heuristic Net Weights, Linear Sized Lp, Timing-driven Relaxed Placement