A massively scaleable decoder architecture for low-density parity-check codes

A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this throughput is achieved without significant bit-error performance degradation. Keywords LDPC Decoder, Parallel Architecture, VLSI, BER/FER, Hardware Scaling

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Anand Selvarathinam, Gwan Choi, Krishna Narayanan, Achal Prabhakar, Euncheol Kim
• Keywords: Architecture Uses Hardware, Hardware Scaling, ISCAS 2003, Low-density Parity-check Codes