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ISCAS
2003
IEEE
103views Hardware» more  ISCAS 2003»
14 years 6 days ago
A massively scaleable decoder architecture for low-density parity-check codes
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
Anand Selvarathinam, Gwan Choi, Krishna Narayanan,...