Measuring the gap between FPGAs and ASICs

This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flipflops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this

• Type: Conference
• Year: 2006
• Where: FPGA
• Authors: Ian Kuon, Jonathan Rose
• Keywords: CMOS FPGA, CMOS Standard Cell, FPGA, FPGA 2006, Measurements