This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power cons...
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
Efficient hardware architectures for the Luffa hash algorithm are proposed in this work. We explore different tradeoffs and propose several architectures, targeting both compac...