Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform

The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall power dissipation is dominated by read and write operations in the memory subsystem. The proposed architecture and computation sequence, called Low-Power Block-Scan, takes into account the EBCOT (Embedded Block Coding with Optimized Truncation) code block size, which reduces the intermediate buffer requirement between the DWT and EBCOT modules. We have modeled the impact of different memory subsystem optimization techniques on the overall memory power for 2D-DWT computation. The proposed model explores the different data access patterns, memory bank partitioning, and custom memory architectures to arrive at a power-efficient DWT architecture.

• Type: Conference
• Year: 2007
• Where: VLSID
• Authors: Rahul Jain, Preeti Ranjan Panda
• Keywords: Computer Architecture, Custom Memory Architectures, Memory Bank Partitioning, Overall Memory Power, VLSID 2007