Memory Organization for Improved Data Cache Performance in Embedded Processors

Code generation for embedded processors creates opportunities for several performance optimizations not applicable for traditional compilers. We present techniques for improving data cache performance by organizing variables declared in embedded code into memory, using specific parameters of the data cache. Our approach clusters variables to minimize compulsory cache misses, and solves the memory assignment problem to minimize conflict cache misses. Our experiments demonstrate significant improvement in data cache performance (average 46% in hit ratios) by the application of our memory organization technique using code kernels from DSP and other domains on the LSI Logic CW4001 embedded processor.

• Type: Conference
• Year: 1996
• Where: ISSS
• Authors: Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
• Keywords: Cache Misses, Data Cache, Data Cache Performance, Hardware, ISSS 1996