A method of redundant clocking detection and power reduction at RT level design

This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clockings which activate registers unnecessarily, we detect these clockings. They are detected from the difference of the numbers of incoming and outgoing data of a register. And then we introduce gated-clock scheme to reduce the power consumption of the circuits using our estimation results. Experimental results demonstrate the accuracy of our method and the effect on power reduction.

• Type: Conference
• Year: 1997
• Where: ISLPED
• Authors: Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, Takashi Kambe
• Keywords: Hardware, ISLPED 1997, Redundant Clockings, Redundant Power, RT Level Design